A Computationally Efficient Pipelined Architecture for 1D/2D Lifting Based Forward and Inverse Discrete Wavelet Transform for CDF 5/3 Filter

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dc.contributor.authorCekli, Serap
dc.date.accessioned2024-07-12T21:44:23Z
dc.date.available2024-07-12T21:44:23Z
dc.date.issued2018en_US
dc.departmentMaltepe Üniversitesien_US
dc.description.abstractIn this study, a simple lifting based pipeline DWT (Discrete Wavelet Transform) architecture is proposed for the operation of the CDF 5/3 (Cohen-Daubechies-Feauveau 5/3) filter. This scalable architecture is faster and capable of fulfilling the transformation utilizing the parallel processing operation units. The symmetric boundary extension method is used at the signal boundaries to obtain the best result in the case of 1D/2D. The proposed architecture utilizes the hardware resources in a quite efficient way by means of the pipeline technique. The architectural design is constituted by using RTL (Register Transfer Level) design process and coded by the Verilog HDL. The proposed architecture is tested for several 1D/2D inputs to examine its operation. The related architecture is synthesized for the FPGA board to check the results. The reverse operation is fulfilled by using the same structure only by changing the shift amounts of the shifting units. The DWT coefficients are calculated on this architecture for the 1D/2D situation. The hardware resources are used effectively by utilizing the constituted architecture in folded structure in the 2D case. Satisfying results have been obtained when the different numbers of parallel processing units are utilized.en_US
dc.identifier.doi10.4316/AECE.2018.02003
dc.identifier.endpage26en_US
dc.identifier.issn1582-7445
dc.identifier.issn1844-7600
dc.identifier.issue2en_US
dc.identifier.scopus2-s2.0-85047844169en_US
dc.identifier.scopusqualityQ3en_US
dc.identifier.startpage17en_US
dc.identifier.urihttps://dx.doi.org/10.4316/AECE.2018.02003
dc.identifier.urihttps://hdl.handle.net/20.500.12415/7720
dc.identifier.volume18en_US
dc.identifier.wosWOS:000434245000003en_US
dc.identifier.wosqualityQ4en_US
dc.indekslendigikaynakWeb of Science
dc.indekslendigikaynakScopus
dc.institutionauthorCekli, Serap
dc.language.isoenen_US
dc.publisherUNIV SUCEAVA, FAC ELECTRICAL ENGen_US
dc.relation.ispartofADVANCES IN ELECTRICAL AND COMPUTER ENGINEERINGen_US
dc.relation.publicationcategoryMakale - Uluslararası Hakemli Dergi - Kurum Öğretim Elemanıen_US
dc.rightsinfo:eu-repo/semantics/openAccessen_US
dc.snmzKY00103
dc.subjectdigital systemsen_US
dc.subjectdiscrete wavelet transformsen_US
dc.subjectmultiprocessing systemsen_US
dc.subjectpipeline processingen_US
dc.subjectprogrammable logic arraysen_US
dc.titleA Computationally Efficient Pipelined Architecture for 1D/2D Lifting Based Forward and Inverse Discrete Wavelet Transform for CDF 5/3 Filteren_US
dc.typeArticle
dspace.entity.typePublication

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