Power-Efficient Viterbi Decoder Architecture and Field Programmeble Gate Arrays Fpga Implementation

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dc.authorid0000-0002-8113-0514en_US
dc.contributor.authorOzbay, Burcu
dc.contributor.authorCekli, Serap
dc.date.accessioned2024-07-12T21:46:19Z
dc.date.available2024-07-12T21:46:19Z
dc.date.issued2018en_US
dc.departmentMaltepe Üniversitesien_US
dc.description.abstractA Viterbi decoder system comprises a convolutional encoder and Viterbi decoder. In general, the code words generated from the input series of convolutional encoder arrive at the decoder through a noisy channel; however, the channel noise can cause corruption of code words. The Viterbi decoder extracts the original input message from the corrupted data using the Viterbi algorithm based on the maximum likelihood principle. A Viterbi decoder mainly comprises four essential units: a branch metrics unit, add-compare-select unit, path metrics unit, and survivor-path memory unit. Related complex calculations are repeated in these units at each clock cycle. In this study, a power- and area-efficient Viterbi decoder architecture that also reduces the computational complexity is proposed. Initially, a hard-decision Viterbi decoder system architecture design for Very Large Scale Integration (VLSI) realization was fulfilled without any further improvement to compare the performance of fundamental and improved designs with respect to power consumption. The initial design constitutes an essential base for the improved power- and area-efficient Viterbi decoder architecture. The improvements were made to achieve the less complex and power-efficient architectural system design. The performance of the proposed architecture was tested by a fieldprogrammable gate array (FPGA) platform, and the results have been reported. The architectural design is described using the Verilog hardware description language for comparing the related tests and performance of FPGA platform.en_US
dc.identifier.citationOzbay, B. ve Cekli, S. (2018). Power-Efficient Viterbi Decoder Architecture and Field Programmeble Gate Arrays Fpga Implementation, Electrica,18(1), s.52-59.
dc.identifier.doi10.5152/iujeee.2018.1809
dc.identifier.endpage59en_US
dc.identifier.issn2619-9831
dc.identifier.issue1en_US
dc.identifier.scopus2-s2.0-85044171531en_US
dc.identifier.scopusqualityQ3en_US
dc.identifier.startpage52en_US
dc.identifier.trdizinid313826en_US
dc.identifier.urihttps://dergipark.org.tr/en/pub/electrica/issue/35704/397850
dc.identifier.urihttps://hdl.handle.net/20.500.12415/7922
dc.identifier.volume18en_US
dc.identifier.wosWOS:000436168500009en_US
dc.identifier.wosqualityN/Aen_US
dc.indekslendigikaynakWeb of Science
dc.indekslendigikaynakScopus
dc.indekslendigikaynakTR-Dizin
dc.language.isoenen_US
dc.publisherISTANBUL UNIV, FAC ENGINEERINGen_US
dc.relation.ispartofELECTRICAen_US
dc.relation.publicationcategoryMakale - Uluslararası Hakemli Dergi - Kurum Öğretim Elemanıen_US
dc.rightsinfo:eu-repo/semantics/openAccessen_US
dc.snmzKY00783
dc.subjectViterbi decoder architectureen_US
dc.subjectFPGA implementationen_US
dc.subjectforward error correctionen_US
dc.titlePower-Efficient Viterbi Decoder Architecture and Field Programmeble Gate Arrays Fpga Implementationen_US
dc.typeArticle
dspace.entity.typePublication

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